The Hong Kong Polytechnic University (PolyU) has announced a breakthrough in transistor technology that could redefine the future of integrated circuits and artificial intelligence hardware. A research team led by Prof. Jianhua Hao, Head of the Department of Physics and Materials and Chair Professor of Materials Physics and Devices at PolyU, has engineered a novel tunnelling field-effect transistor (TFET) using 2D nanomaterials. This innovation overcomes the physical 'Boltzmann limit', a barrier that has constrained the energy efficiency of conventional transistors for decades.
Conventional transistors rely on thermionic emission of electrical charges, which requires a minimum gating voltage of 60 millivolts (mV). This fundamental limit makes subthreshold swing (SS) values below 60 mV per decade impossible at room temperature, restricting progress in high-performance electronics. By leveraging quantum tunnelling, the new TFET breaks this boundary, achieving SS values well below the 60 mV decade⁻¹ limit. Operating at room temperature on silicon substrates, the device requires a gate-voltage range of only 160 mV—far lower than the 800 mV originally needed. This dramatic reduction in voltage translates to significantly lower power consumption, a critical factor for next-generation AI chips and portable electronics.
The team created an ultra-thin heterostructure of 2D bismuth and indium selenide alternating layers using pulsed laser deposition. By exercising precise control over the layer structure, the normally semi-metallic bismuth transforms into a semiconductor in 2D form, allowing charge carriers to tunnel efficiently into indium selenide through the quantum tunnelling mechanism. This design not only achieves high output current but also maintains an exceptionally high ON/OFF current ratio, addressing a long-standing challenge in experimental TFETs. This combination enables the device to drive multiple downstream logic gates and diminish circuit delay, a key requirement for practical integrated circuits.
The research, published in the prestigious journal Science, was conducted in collaboration with the National University of Singapore, The Hong Kong University of Science and Technology, Peking University, and the Singapore University of Technology and Design. Prof. Hao stated, 'By adopting quantum tunnelling, our TFET breaks through this boundary, paving the way for ultra-low-power, high-performance integrated circuits essential for emerging AI chips and advanced semiconductor applications.'
This breakthrough comes at a time when the semiconductor industry is facing physical limits in miniaturization and energy efficiency. The demand for more powerful yet energy-efficient processors is escalating, driven by the proliferation of AI, IoT, and mobile devices. The TFET's ability to operate at ultra-low voltages without sacrificing performance could lead to significant advancements in battery life and computational capabilities. Moreover, the use of 2D materials on silicon substrates suggests compatibility with existing manufacturing processes, potentially accelerating commercial adoption.
The implications extend beyond computing. Energy-efficient transistors are crucial for reducing the carbon footprint of data centres, which are major consumers of electricity worldwide. By enabling lower power consumption, this technology could contribute to more sustainable digital infrastructure. The next steps for the research team involve scaling up the technology and exploring integration with current chip fabrication methods. As the industry looks for alternatives to conventional CMOS technology, this TFET represents a promising avenue for future electronics.
